Q.4. (a): Minimise the following logic expression using Karnaugh map.
Solution: By using six variables Karnaugh map, we can minimize the give logic as-
the obtained minimized logic function is -
F = CE'F + A'B'C'DEF' + A'BC'D'E + A'BD'EF
Q.4. (b): A Tri-state logic gate circuit is shown. Explain the working of the circuit when (i) control is LOW and when (ii) control is HIGH. What are the applications of the circuit?
f(A, B, C, D,E, F) = ∑m(6, 9, 13, 18, 19, 25, 27, 29, 41, 45, 57, 61)
Solution: By using six variables Karnaugh map, we can minimize the give logic as-
the obtained minimized logic function is -
F = CE'F + A'B'C'DEF' + A'BC'D'E + A'BD'EF
Q.4. (b): A Tri-state logic gate circuit is shown. Explain the working of the circuit when (i) control is LOW and when (ii) control is HIGH. What are the applications of the circuit?
Solution: When control is low, as it leads to 0 input to at least one emitter of Q1 will forward bias the corresponding base emitter junction, causing current to flow out of that emitter. This causes the stored base charge of Q2 to discharge through Q1, during Q2 into cut off. Now that Q2 is cut off, current from Vcc will be diverted to the base of Q4 through R3, causing Q4 to saturate. On the other hand, the base of Q3 will be deprived of current, causing Q3 to go into cut off. With Q3 in cut off and Q4 in saturation, the output Vo is pulled up to logic 1 or closer to Vcc.
When control is High, and suppose the input applied is also High, hence Q1 reverse biases both base emitter junctions, causing current to flow through R1 into the base of Q2, which is drawn into saturation. When Q2 starts conducting, the stored base charge of Q4 dissipate through Q2 collector, driving Q4 in cut off. On the other hand, current flows into the base of Q3, causing it to saturate and pull down the output voltage Vo to logic 0 or near ground. Also since Q4 is in cut off, no current will flow from Vcc to the output, keeping it at logic 0. Note that Q2 always provides complementary inputs to the base of Q4 and Q3, such that Q4 and Q3 always operate in opposite regions, except during momentary transition between region.
Hence, this circuit will work as NAND gate, considering Data input and Control as the two inputs of the circuit.
Q.4.(c): What is wired logic ? What are the applications of open collector TTL gates? For the circuit shown find expression for Y. What logical function is performed by the circuit?
Solution:
In circuit mentioned in the question, is a wired AND connection with two inputs. The expression for Y is-
Q.4.(c): What is wired logic ? What are the applications of open collector TTL gates? For the circuit shown find expression for Y. What logical function is performed by the circuit?
Solution:
Wired logic:
A wired logic connection is a logic gate that implements Boolean algebra (logic) using only passive components such as diodes and resisters. A wired logic connections can create an AND or OR gate. The limitations are the inability to create NOT gate and the lack of level restoration.Application of Open collector TTL gates:
Some applications require to connect the output of several devices together to drive a single signal. For these applications, consider open collector outputs in order to avoid bus fight. Bus fight occurs when different gates attempts to drive a signal to different logic states. Unlike outputs that drive signals either High or Low, open collector output either drive outputs Low or let them float. If several open collector outputs are attached to the same signal, the signal will go Low if any of the outputs is Low. But if we need to drive a logic High, it is needed to add an external resistor, called pull up resistor.In circuit mentioned in the question, is a wired AND connection with two inputs. The expression for Y is-
Y = (AB)'.(A'B')' = (A' + B')(A + B) = A'B + AB'
Hence, the given circuit stands for EX-OR gate.
No comments:
Post a Comment