Modern Processor Design by John Paul Shen and Mikko H. Lipasti : Exercise 2.17 Solution

Q.2.17: The MIPS pipeline shown in Table 2-7 employs a two-phase clocking scheme that makes efficient use of a shared TLB, since instruction fetch accesses the TLB in phase one and data fetch accesses in phase two. However, when resolving a conditional branch, both the branch target address and the branch fall-through address need to be translated during phase one--in parallel with the branch condition check in phase one of the ALU stage--to enable instruction fetch from either the target or the fall-through during phase two. This seems to imply a dual-ported TLB. Suggest an architected solution to this

problem that avoids dual-porting the TLB.

Sol: Two solutions are possible. In either case, the instruction translation for the branch instruction is reused for the subsequent fetch. The first solution requires that all branch targets lie within the same physical page as the branch instruction. Hence, the physical page number of the branch instruction can be reused with the branch target. The compiler and programmer must take special care to ensure that this is the case. Alternatively, the branch fall-through path can be restricted to be on the same page. In this scenario, the pipeline reuses the physical page number of the branch when fetching the fall-through path, and uses the TLB to translate the target address. This restriction is simpler, since it only forbids the compiler or programmer from placing a branch instruction at the end of a physical page. Whenever a branch does fall into such a location, the compiler can pad it with NOPs to place it on the next page.