Ex 1.6 and 1.7 Solution: Modern Processor Design by John Paul Shen and Mikko H. Lipasti :

Q.1.6: A program's run time is determined by the product of instructions per program, cycles per instruction, and clock frequency. Assume the following instruction mix for a MlPS-like RISC instruction set:  15% stores, 25% loads, 15% branches, and 35% integer arithmetic, 5% integer shift, and 5% integer multiply. Given that load instructions require two cycles, branches require four cycles, integer ALU instructions require one cycle, and integer multiplies require ten cycles, compute the overall CPI.

Solution: 

                 CPI computation:

                          Type                      Mix          Cost          CPI

                          Load                       25%            2             0.5 

                          Store                      15%            1            0.15

                          Branch                   15%            4             0.6

                          Integer arithmetic   35%            1            0.35

                          Integer shift            5%              1            0.05

                          Integer multiply       5%             10           0.5 

                                

                          Total :                                                    2.15 

Q.1.7: Given the parameters of Problem 6, consider a strength-reducing optimization that converts multiplies by a compile-time constant into a sequence of shifts and adds. For this instruction mix, 50% of the multiplies can be converted to shift-add sequences with an average length of three instructions. Assuming a fixed frequency, compute the change in instructions per program, cycles per instruction, and overall program speedup.

Solution: 

             CPI computation :

                Type                          Old Mix        New Mix        Cost        CPI

                store                             15%              15%               1           0.15

                load                              25%               25%               2          0.50

                branch                          15%               15%               4          0.60

                integer & shift               40%               47.5%            1          0.475

                multiply                         5%                 2.5%            10          0.25

                Total                           100%              105%    1.975/105% = 1.88

There are 5% more instructions per program, the CPI is reduced by 12.5% to 1.88, and overall speedup is = 2.15/1.975 = 1.089    (or 8.9%.)

The Evolution of Microprocessors

In 1971, the first microprocessor, the Intel 4004 was introduced. It was just 4 bit processor possessing approximately 2300 transistors with clock frequency around just over 100 KHz. It was used specially in calculators. But now, we can see the rapid change rather evolution in the microprocessors. We can see high end microprocessors possessing transistors up to 100 million and clock frequency is reaching up to 2 GHz. And such microprocessors finds their application in supercomputer system, cloud computing, powerful client and server system that populate the internet. Its just a start...we can expect microprocessors clocked with 10 GHz and containing around thousands of million of transistors within few years.

As quoted by Intel Corporation-  

 "The microprocessor is one of the unsung heroes of the modern era. Like the car designer whose vehicle gives the racing driver glory, the microprocessor makes quite incredible things possible all over the world. Each year we benefit from faster and more efficient performance which improves not just computing, but also numerous fields from retail and industry to agriculture and vehicle safety. This year, the humble microprocessor celebrates its 40th birthday. Since 1971, it has become the brain of literally millions of devices - without the microprocessor they would not have existed." 

This DOCUMENT is designed by Intel Corporation and is enough to explain the growth and evolution of microprocessors and its contribution towards it.

Next Topic:

Q.1.8: Recent processors like the Pentium 4 processors do not implement single-cycle shifts. Given the scenario of Problem 7, assume that s = 50% of the additional integer and shift instructions introduced by strength reduction are shifts, and shifts now take four cycles to execute. Recompute the cycles per instruction and overall program speedup. Is strength reduction still a good optimization?

Q.1.9: Given the assumptions of Problem 8, solve for the break-even ratio s (percentage of additional instructions that are shifts). That is, find the value of s (if any) for which program performance is identical to the baseline case without strength reduction (Problem 6).

Q.1.10: Given the assumptions of Problem 8, assume you are designing the shift unit on the Pentium 4 processor. You have concluded there are two possible implementation options for the shift unit: 4-cycle shift latency at a frequency of 2 GHz, or 2-cycle shift latency at 1.9 GHz. Assume the rest of the pipeline could run at 2 GHz, and hence the 2-cycle shifter would set the entire processor’s frequency to 1.9 GHz. Which option will provide better overall performance?

SOLUTION